Advanced Nano CMOS Platform using Carrier-Transport-Enhanced Channels

It has been well recognized that, under sub-100 nm regime, conventional device scaling concept has confronted with several physical and essential limitations. Therefore, any new device engineering to realize advanced CMOS by overcoming these difficulties is strongly needed. A group of theses new device technologies called the technology boosters can be classified mainly into three categories, gate stack engineering, source engineering and channel engineering. Particularly, the channel engineering includes carrier-transport-enhanced channels aiming at high current drive and multi-gate channels aiming at high immunity for short channel effects. Among them, the carrier-transport-enhanced channels, typically seen in strained-Si channels, are recently becoming more important.