Title :
Effects of Through-BOX Vias on SOI MOSFETs
Author :
Chen, C.L. ; Chen, C.K. ; Wyatt, P.W. ; Gouker, P.M. ; Burns, J.A. ; Knecht, J.M. ; Yost, D.-R. ; Healey, P. ; Keast, C.L.
Author_Institution :
Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA
Abstract :
The metal-filled vias through the buried oxide are integrated with silicon-on-insulator (SOI) MOSFETs. The FET temperature, measured directly using integrated junction diodes, can be lowered by as much as 25degC with these vias. In addition to enhanced DC characteristics, lowered gate resistance and output conductance further improve the RF performance and the extent of improvement is dependent on the FET design.
Keywords :
MOSFET; integrated circuit design; semiconductor diodes; silicon-on-insulator; FET design; buried oxide; integrated junction diodes; metal-filled vias; silicon-on-insulator MOSFET; Contacts; Diodes; Electrical resistance measurement; Etching; FETs; MOSFETs; Radio frequency; Silicon on insulator technology; Temperature measurement; Temperature sensors;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530815
