Title :
Low-Leakage SMARTMOS 10W Technology At 0.13μm Node with Optimized Analog, Power and Logic Devices for SOC Design
Author :
Yang, Hongning ; Min, Won-Gi ; Lin, Xin ; Newenhouse, Veronique ; Huber, John ; Xu, Hongzhong ; Zhang, Zhihong ; Peterson, Bill ; Zuo, Jiang-Kai
Author_Institution :
SMARTMOS Technol. Center, Freescale Semicond., Inc., Tempe, AZ
Abstract :
SMARTMOS 10 W technology, which was developed based on 0.13-micron technology node, combines optimized power, analog and digital devices for wireless and consumer applications. As compared to the current state-of-the-art technologies, significant size shrink in power devices is achieved for cost reduction while the leakage is lowered by more than 20 times to minimize power consumption. Also, the technology doubles the performance of analog matching across FETs, resistors and capacitors. This technology is an excellent fit for all portable applications in which device size, battery life, sound quality and overall integration capability are key considerations.
Keywords :
MOS analogue integrated circuits; MOS logic circuits; integrated circuit design; power MOSFET; system-on-chip; MOSFET; SOC design; analog matching; battery life; cost reduction; logic devices; low-leakage SMARTMOS technology; optimized analog devices; overall integration capability; power 10 W; power consumption; power devices; size 0.13 mum; sound quality; Capacitors; Costs; Degradation; Design optimization; Human computer interaction; Integrated circuit technology; Logic devices; MOS devices; MOSFETs; Voltage;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530822
