Title :
Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory
Author :
Kailiang Lu ; Rajendran, Bipin ; Happ, Thomas D. ; Ng, Ricky M Y ; Lung, Hsiang-Lan ; Lam, Chung ; Chan, Mansun
Author_Institution :
Dept. of Electron. & Comput. Eng., HKUST, Hong Kong
Abstract :
In this work, a compact physical model with diode access devices for PCM technology is developed and verified with extensive 2-D and 3-D device simulations. The choice of design parameters allows the operation of the diode access device to serve as a bipolar junction transistor (BJT) for the same physical structure. The PCM array design with these devices is optimized for the 90 nm, 45 nm and 32 nm technology nodes based on this compact model and further verified by 3-D numerical device simulation.
Keywords :
bipolar transistors; numerical analysis; p-n junctions; phase change materials; 3D numerical device simulation; BJT; bipolar junction transistor; compact physical model; diode array design optimized scaling; node phase change memory; Circuit simulation; Design optimization; Diodes; Doping; Numerical simulation; Phase change materials; Phase change memory; Phased arrays; Semiconductor device modeling; Semiconductor process modeling;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530833
