Pin assignment with timing consideration [VLSI]

In this paper we consider a pin assignment problem with circuit performance consideration. We are given a set of nets and their corresponding pins. Each pin of the nets has its own available slots to be placed. Also within each net there is a delay bound from source pin to each sink pin. Our objective is to assign a slot for each pin such that timing delay and wire length are minimized while satisfying the source to sink timing constraints. We first consider the single net case and present a polynomial time algorithm to solve the problem optimally. Then we extend this single net case together with weighted bipartite matching algorithm to solve the general multi-net case. Our algorithms can be applied to the pin assignment in floor planning and also the pin permutation in standard cell design. We ran our algorithms on some test circuits. The average performance improvement is 12% and total wire length reduction is 6%