1T2R Structure with Cross-Spacer for High-Density Phase Change Memory

Author

Lee, Chain-Ming ; Chen, Chih-Wei ; Chen, Wei-Su ; Chao, Der-Sheng ; Chen, Ming-Jung ; Yen, Philip H. ; Chen, Fred ; Kao, Ming-Jer ; Tsai, Ming-Jinn

Author_Institution

EOL/Ind. Technol. Res. Inst., Hsinchu

fYear

2008

Firstpage

136

Lastpage

137

Abstract

A novel 2-bit per cell architecture is proposed for high density phase change memory (PCM) array. One transistor controls one pair of cross-spacer type memory cells through a common bottom electrode. Such configuration so-called "chain structure" shows advantages in either enhanced memory density or enhanced current driving capability. In this paper, a 1 k bits test array is demonstrated, in which a minimum reset current about 0.4 mA is provided by a 3.3 V NMOS transistor (0.18 um CMOS technology).

Keywords

CMOS memory circuits; phase changing circuits; 1T2R structure; 2-bit per cell architecture; CMOS technology; NMOS transistor; PCM array; chain structure; common bottom electrode; cross-spacer type memory cells; current 0.4 mA; high-density phase change memory; size 0.18 mum; transistor controls; voltage 3.3 V; CMOS technology; Diodes; Electrodes; Lithography; MOSFET circuits; Phase change materials; Phase change memory; Phased arrays; Space vector pulse width modulation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530834

Filename

4530834