Title :
Integration of high-k/metal gate stacks for CMOS application
Author :
Chen, D.Y. ; Lin, C.T. ; Hsu, Y.R. ; Chang, C.H. ; Wang, H.Y. ; Chiu, Y.S. ; Yu, C.H.
Author_Institution :
Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Hsinchu
Abstract :
Integration of high-k/metal gate stacks has been discussed in this paper. Pre-gate clean, interfacial oxide treatment, high-k and metal film deposition were investigated for optimized Jg-EOT. Various approaches such as HF vapor clean, surface hydroxylation treatment, and metal gate modification (such as interface treatment and high density top layer) were employed to improve the electrical properties. Electrical characterization (C-V, I-V) and material analysis (TEM, XPS) were conducted to examine the effects of these approaches on high-k/metal gate stacks.
Keywords :
CMOS integrated circuits; X-ray photoelectron spectra; electronic density of states; hafnium compounds; high-k dielectric thin films; metal-insulator boundaries; surface cleaning; tantalum compounds; transmission electron microscopy; C-V characterization; CMOS application; HF vapor clean; I-V characterization; TEM; TaN-HfO2; XPS; electrical characterization; electrical properties; high density top layer; high-k deposition; high-k/metal gate stacks; interface treatment; interfacial oxide treatment; metal film deposition; pregate cleaning; surface hydroxylation treatment; Atherosclerosis; Channel bank filters; Gate leakage; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Tin; Tunneling; Voltage;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530840
