Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering

Author

Deng, Jie ; Wei, Lan ; Chang, Li-Wen ; Kim, Keunwoo ; Chuang, Ching-Te ; Wong, H. S Philip

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA

fYear

2008

Firstpage

159

Lastpage

160

Abstract

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.

Keywords

capacitance; integrated circuit interconnections; scaling circuits; wiring; device parasitic resistance; interconnect wiring capacitance; parasitic capacitance; parasitics engineering; selective device footprint scaling; technology boosters; technology roadmap; technology scaling; Capacitive sensors; Circuit simulation; Delay; High K dielectric materials; Integrated circuit interconnections; Inverters; Lithography; Parasitic capacitance; Plugs; Polymers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530846

Filename

4530846