Title :
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance
Author :
Wei Wei ; Lombardi, Floriana ; Namba, Kazuteru
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A SER analysis of these cells is also pursued. An extensive evaluation and comparison of different schemes are presented.
Keywords :
SRAM chips; integrated circuit design; leakage currents; low-power electronics; power consumption; radiation hardening (electronics); NV memory cells; SER analysis; SEU; gate leakage current reduction; low power nonvolatile memory cells; low-power hardened NVSRAM cell designs; nonvolatile storage; positive ground level voltage; power consumption; single event upset tolerance; Leakage currents; Nonvolatile memory; Power dissipation; Random access memory; Resistance; Single event upsets; Transistors; HSPICE; Leakage reduction; Memory design; NVSRAM; Nonvolatile Memory; Radiation hardening; Resistive RAM;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4799-6154-2
DOI :
10.1109/DFT.2014.6962061
