DocumentCode
159468
Title
Characterization of data retention faults in DRAM devices
Author
Bacchini, Angelo ; Rovatti, Marco ; Furano, Gianluca ; Ottavi, Marco
Author_Institution
Dept. of Electron. Eng., Univ. of Rome Tor Vergata, Rome, Italy
fYear
2014
fDate
1-3 Oct. 2014
Firstpage
9
Lastpage
14
Abstract
Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it is still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition. As these failures could be related to the memory cell´s ability to retain its stored charge, an empirical characterization of DRAM data retention time was performed within this study. Retention time information was collected from SDRAM devices from two different vendors to evaluate the impact of four different factors (temperature, data background, previous charge level and variable retention time) on DRAM cells retention time. Gathered results can be useful in defining enhanced test procedures for the early detection of data retention faults.
Keywords
DRAM chips; integrated circuit testing; DRAM cell retention time; DRAM data retention time; DRAM errors; DRAM subsystem; SDRAM devices; data retention faults; dynamic random access memory; mass memories; memory address; memory cell; retention time information; Capacitors; Random access memory; Solids; Temperature dependence; Temperature distribution; Temperature measurement; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on
Conference_Location
Amsterdam
Print_ISBN
978-1-4799-6154-2
Type
conf
DOI
10.1109/DFT.2014.6962069
Filename
6962069
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