Title :
A probabilistic analysis of resilient reconfigurable designs
Author :
Malek, Alirad ; Tzilis, Stavros ; Khan, Danish Anis ; Sourdis, Ioannis ; Smaragdos, Georgios ; Strydis, Christos
Author_Institution :
Comput. Sci. & Eng. Dept., Chalmers Univ. of Technol., Gothenburg, Sweden
Abstract :
Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising a System-on-Chip can be partitioned into a handful of substitutable units interconnected with reconfigurable wires to allow isolation and replacement of faulty parts. This paper offers a probabilistic analysis of reconfigurable designs estimating for different fault densities the average number of fault-free components that can be constructed as well as the probability to guarantee a particular availability of components. Considering the area overheads of reconfigurability, we evaluate the resilience of various reconfigurable designs with different granularities. Based on this analysis, we conduct a comprehensive design-space exploration to identify the granularity mixes that maximize the fault-tolerance of a system. Our findings reveal that mixing fine-grain logic with a coarse-grain sparing approach tolerates up to 3× more permanent faults than component redundancy and 2× more than any other purely coarse-grain solution. Component redundancy is preferable at low fault densities, while coarse-grain and mixed-grain reconfigurability maximize availability at medium and high fault densities, respectively.
Keywords :
fault tolerance; integrated circuit design; logic circuits; logic design; probability; reconfigurable architectures; system-on-chip; coarse-grain reconfigurability; coarse-grain sparing approach; design-space exploration; fault densities; fault tolerance; fault-free components; fine-grain logic; hardware components; mixed-grain reconfigurability; permanent faults; probabilistic analysis; rconfigurable hardware; reconfigurable designs; reconfigurable wires; system-on-chip; Availability; Circuit faults; Fault tolerant systems; Pipelines; Redundancy; Wires;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4799-6154-2
DOI :
10.1109/DFT.2014.6962074