Unifying scan compression

Author

Bahl, Swapnil ; Rungta, Shreyans ; Khullar, Shray ; Kapur, R. ; Chandra, Aniruddha ; Talluto, Salvatore ; Notiyath, Pramod ; Rajagopalan, Ajit

Author_Institution

Technol. R&D, ST Microelectron., India

fYear

2014

fDate

1-3 Oct. 2014

Firstpage

191

Lastpage

196

Abstract

STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.

Keywords

automatic test pattern generation; boundary scan testing; design for testability; integrated circuit testing; DFTMAX Ultra technology; STMicroelectronics; unified solution; unifying scan compression; Automatic test pattern generation; Codecs; Discrete Fourier transforms; Pins; Pipeline processing; Shift registers; Scan Compression; Scan test; low pin count test;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on

Conference_Location

Amsterdam

Print_ISBN

978-1-4799-6154-2

Type

conf

DOI

10.1109/DFT.2014.6962079

Filename

6962079