Title :
Optimal design of interleaved synchronous buck converter at high slew-rate load current transients
Author :
Miftakhutdinov, Rais
Author_Institution :
Power Manage. Products, Texas Instrum. Inc., Dallas, TX, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
An interleaved synchronous-buck converter for powering future microprocessors is analyzed at high slew-rate load-current transients. Optimal design procedure is suggested based on derived equations for any number of channels. Output filter design example for popular 12-V input, 1.5-V, 50-A regulator is presented to illustrate analysis and compare different number of channels and type of capacitors for this application
Keywords :
DC-DC power convertors; capacitors; computer power supplies; transient analysis; 1.5 V; 12 V; 50 A; capacitors; high slew-rate load-current transients; interleaved synchronous-buck converter; microprocessors powering; optimal design procedure; output filter design; regulator; Buck converters; Capacitors; Filters; Microprocessors; Power supplies; Power system modeling; Steady-state; Transient analysis; Transient response; Voltage;
Conference_Titel :
Power Electronics Specialists Conference, 2001. PESC. 2001 IEEE 32nd Annual
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-7067-8
DOI :
10.1109/PESC.2001.954366
