DocumentCode
159490
Title
A data recomputation approach for reliability improvement of scratchpad memory in embedded systems
Author
Sayadi, Hossein ; Farbeh, Hamed ; Monazzah, Amir Mahdi Hosseini ; Miremadi, Seyed Ghassem
Author_Institution
Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
fYear
2014
fDate
1-3 Oct. 2014
Firstpage
228
Lastpage
233
Abstract
Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.
Keywords
cache storage; embedded systems; error correction codes; integrated circuit reliability; radiation hardening (electronics); ECCs; MBUs; SPM cells; SPM protection; cache memory; data recomputation approach; embedded processors; embedded systems; energetic particle strikes; error correcting code; memory protection techniques; minimum overheads; multiple-bit upsets; reliability improvement; scratchpad memory; soft error fraction; Algorithms; Arrays; Energy consumption; Error correction; Error correction codes; Program processors; Reliability; Data Recomputation; Embedded Systems; Error Correction; Reliability; Scratchpad Memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on
Conference_Location
Amsterdam
Print_ISBN
978-1-4799-6154-2
Type
conf
DOI
10.1109/DFT.2014.6962091
Filename
6962091
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