Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

Author

Backer, Jerry ; Hely, D. ; Karri, Ramesh

Author_Institution

Polytech. Sch. of Eng., New York Univ., New York, NY, USA

fYear

2014

fDate

1-3 Oct. 2014

Firstpage

52

Lastpage

56

Abstract

Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn´t require modifications to the SoC.

Keywords

design for testability; invasive software; system-on-chip; DfT infrastructure; IEEE 1500 DfT; SoC; design for test infrastructure; hardware overhead; hardware trojans; malicious software; observability features; plug-and-play features; security monitoring; security threats; systems-on-chip; Engines; Hardware; IP networks; Monitoring; Pins; Security; System-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on

Conference_Location

Amsterdam

Print_ISBN

978-1-4799-6154-2

Type

conf

DOI

10.1109/DFT.2014.6962098

Filename

6962098