Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn´t require modifications to the SoC.