Title :
A weight-adjustable hardware accelerator board for DTCNN implementation and application
Author :
Zhang, Liming ; Wang, Wei ; Jiang, Ke
Author_Institution :
Dept. of Electron. Eng., Fudan Univ., Shanghai, China
Abstract :
A new method which uses only comparison and matching circuits to implement the neural net is introduced. The digital accelerator board combined with FPGA for simulating the behavior of discrete-time cellular neurons is presented in this paper. Via host computer the connected-weights can be modified in the hardware nearly arbitrarily. The network can realize various functions if the weights satisfy some conditions. The experiments show that the computation speed exceeds software implementation by 70-1000 limes. Finally, an application of feature extraction on handwritten characters recognition system shows the efficiency of the hardware with low cost
Keywords :
cellular neural nets; character recognition; feature extraction; field programmable gate arrays; handwriting recognition; DTCNN implementation; FPGA; digital accelerator board; discrete-time cellular neurons; feature extraction; handwritten characters recognition system; neural net; software implementation; weight-adjustable hardware accelerator board; Application software; Character recognition; Circuit simulation; Computational modeling; Costs; Feature extraction; Field programmable gate arrays; Hardware; Neural networks; Neurons;
Conference_Titel :
Cellular Neural Networks and their Applications, 1996. CNNA-96. Proceedings., 1996 Fourth IEEE International Workshop on
Conference_Location :
Seville
Print_ISBN :
0-7803-3261-X
DOI :
10.1109/CNNA.1996.566564
