Title :
Low-power multiple-valued SRAM logic cells using single-electron devices
Author :
Syed, Naila ; Chen, Chunhong
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
Abstract :
This paper presents single electron tunneling (SET) based static memory cells for multiple-valued logic applications. All simulations are conducted using Monte Carlo simulation tools. In particular, a ternary SRAM cell is designed using the proposed architecture with standby power consumption of 0.98nW and logic margin of 270mV at temperature of 77K.
Keywords :
Monte Carlo methods; SRAM chips; logic circuits; low-power electronics; power consumption; single electron devices; ternary logic; tunnelling; Monte Carlo simulation tool; SET based static memory cells; low-power multiple-valued SRAM logic cells; multiple-valued logic application; power 0.98 nW; single electron tunneling; single-electron device; standby power consumption; temperature 77 K; ternary SRAM cell; voltage 270 mV; Computer architecture; Power demand; Power dissipation; Random access memory; Switches; Temperature; Tunneling; SRAM cell; Single electron devices; low power; multiple-valued logic; negative differential conductance;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on
Conference_Location :
Birmingham
Print_ISBN :
978-1-4673-2198-3
DOI :
10.1109/NANO.2012.6321901
