ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

Author

Prysby, Daniel ; Younce, Richard ; Duhachek, J. ; Baughman, David

Author_Institution

Texas Instruments, Arlington Heights, IL, USA

fYear

1993

Firstpage

100

Lastpage

103

Abstract

The design of a multi-channel, single-chip, adaptive echo canceller for T1 and E1 long-distance telecommunications networks is described. The ECHO2 chip required a novel architecture to achieve the throughput necessary to process multi-channels and end-paths of up to 128 msec delay. The design was implemented in Texas Instruments TLM CMOS EPICIZ 1 μm process and TSC700 standard cell technology. Several MegaModules were used including a TMS320C10 cDSP, two 16 by 16 Multiplier-Accumulators and 2 Compiler Cell RAMs

Keywords

CMOS digital integrated circuits; VLSI; adaptive signal processing; application specific integrated circuits; cellular arrays; convolution; digital signal processing chips; echo suppression; integrated circuit design; 1 micron; 128 ms; ASIC; CMOS EPICIZ; ECHO2; LMS adaptive filtering algorithm; MegaModules; TSC700 standard cell; VLSI ECHO canceller; adaptive echo canceller; compiler cell RAMs; embedded TMS320C10 DSP; hard-wired convolution processor; long-distance telecommunications networks; multi-channel; multiplier-accumulators; single-chip; Adaptive filters; Application specific integrated circuits; Convolution; Digital signal processing; Echo cancellers; Instruments; Partitioning algorithms; Signal processing algorithms; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410818

Filename

410818