Title :
Impact of process variants on SEU tolerance of CMOS/SOS circuits
Author :
Brucker, G.J. ; Strater, K. ; Veloric, H.
Author_Institution :
GE Astro Space Div., Princeton, NJ, USA
Abstract :
Summary form only given. The impact of several process variants on single-event-upset (SEU) tolerance of the RCA/GE 6167/RZ, 16 K CMOS/SOS SRAM was determined. The RAMs were fabricated with a 3-μm gate process. In epitaxial films consisting of three crystal structures and two p impurity profiles. The devices were evaluated in the SEU test facility at Brookhaven Laboratory. Although some test cells showed improvements in total dose hardness, there was no degradation in SEU tolerance. The SEU tolerance of a CMOS and CMOS/SOS error detection and correction circuit was also evaluated. The circuits were gate arrays processed with a 1.2-μm gate process. The circuit could not be upset up to a cross section of 149 MeV-cm2/mg. The CMOS circuit has an error rate ~4E-7/day. The SEU test data are summarized in a table
Keywords :
CMOS integrated circuits; circuit reliability; error correction; error detection; errors; integrated circuit technology; integrated memory circuits; logic arrays; radiation hardening (electronics); random-access storage; 1.2 micron; 16 kbit; 3 micron; CMOS/SOS circuits; RCA/GE 6167/RZ; SEU tolerance; SRAM; Si-Al2O3; error detection/correction circuit; gate arrays; logic circuits; monolithic IC; process variants; reliability; single-event-upset; static RAM; total dose hardness; CMOS process; Circuit testing; Error correction; Impurities; Random access memory; Semiconductor films; Single event upset; Test facilities; Transconductance; Voltage control;
Conference_Titel :
SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE
Conference_Location :
St. Simons Island, GA
DOI :
10.1109/SOI.1988.95443
