Reduction of threshold voltage at the SOI MOSFET sidewalls due to charge sharing with the front and back interfaces

Summary form only given, as follows. MOSFETs fabricated on silicon-on-insulator substrates have two additional parasitic MOS transistors in parallel with the main front channel. The back-gate transistor is controlled by the substrate with the buried oxide as the dielectric. The sidewall transistor is controlled by the front-gate through the sidewall dielectric. Five-terminal SOI MOSFETs were characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with body at the front and back interfaces can be explained by the standard bulk body bias equation, but the threshold voltage shift at the sidewall is smaller than that expected from this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model has been developed which accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation at large body biases