Title :
A clock frequency doubler using a passive integrator and emitter-coupled comparator circuit
Author :
Saavedra, Carlos E. ; Zhang, Yang
Author_Institution :
Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont., Canada
Abstract :
A frequency doubler circuit is described using an integrator circuit, a comparator, and an exclusive OR (XOR) gate for use with clock waveforms. The integrator and comparator circuits delay the incoming signal by T/4 (90°), where T is the clock period. When the delayed and the original signal enter the XOR gate, the output is a signal with twice the frequency of the clock. This circuit concept was verified experimentally using a 1 MHz input signal, which resulted in a 2 MHz output signal.
Keywords :
comparators (circuits); delay circuits; frequency multipliers; integrating circuits; logic gates; network synthesis; 1 MHz; 2 MHz; XOR gate; clock frequency doubler; clock waveforms; delay circuit; digital communications; emitter-coupled comparator circuit; exclusive OR gate; passive integrator circuit; Circuits; Clocks; Frequency conversion; Phase detection; Phase frequency detector; Phase locked loops; Propagation delay; Signal generators; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Electrical and Computer Engineering, 2004. Canadian Conference on
Print_ISBN :
0-7803-8253-6
DOI :
10.1109/CCECE.2004.1344975
