Designing and simulation of full adder cell using FINFET technique

This paper proposes a 1-Bit full adder cell using Double Gate FINFET (Fin Shaped Field Effect Transistor) at 45nm CMOS technology. The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented in this paper. Double Gate FINFET technique which decreases the process variation on 1-bit Full Adder is presented in this paper; the key of Double Gate FINFET technique is applied on 1-bit Full Adder is to reduce the operating power, leakage power and leakage current. We investigate the use of Double Gate FINFET technology provides low leakage and high performance operation by utilizing high speed and low thresh hold voltage transistors for logic cells. Which show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 20ns access time and frequency 0.05GHz provide 45nm CMOS process technology with 0.7V power supply is employed to carry out 1-bit Full Adder