CMOS/SOS circuits for space applications

Author

Veloric, H.S. ; Green, R.

fYear

1988

Firstpage

12

Abstract

Summary form only given. The authors have investigated the capability of CMOS/SOS circuits fabricated in a 1.25-μm DLM technology. The circuits included delay chains, a shift register, gate arrays, and a 8KX8 SRAM. Accurate circuit simulations were possible using the device parameters and current modeling procedures. The preradiation and postradiation performances of circuits were compared to their calculated capability. This included performance under transient radiation conditions. 64K SRAMS were fabricated with an access time under 20 ns. These circuits have demonstrated total dose tolerance in excess of 1 Mrad (Si) and transient upset of 5×10¹¹ rad (Si)/s

Keywords

CMOS integrated circuits; aerospace instrumentation; integrated logic circuits; integrated memory circuits; metallisation; radiation hardening (electronics); 1.25 micron; 1E6 rad; 20 ns; 5E11 rad; 64 kbit; CMOS/SOS circuits; DLM technology; SRAM; access time; circuit simulations; current modeling procedures; delay chains; device parameters; device technology double level metal; gate arrays; performance under transient radiation conditions; postradiation performances; shift register; space applications; total dose tolerance; transient upset; CMOS memory circuits; CMOS technology; Circuit simulation; Delay; Microprocessors; Neutrons; Radiation hardening; Random access memory; Registers; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE

Conference_Location

St. Simons Island, GA

Type

conf

DOI

10.1109/SOI.1988.95457

Filename

95457