Performance analysis of ultra deep sub micron and deep sub micron technology using complementary metal oxide semiconductor inverter

The CMOS technology attained remarkable progress and advances. This progress has been achieved by downsizing of the MOSFETs. The dimensions of the MOSFETs were scaled by factor s, which has historically found to be 0.7. In VLSI technology, power and delay analysis have become crucial design concern. This paper emphasizes the comparative study of delay, average power and leakage power of CMOS inverter in DSM and UDSM range. This study shows variation of delay, average power and leakage power by diminishing from one technology to another. The simulation results are taken for 180nm in DSM range and 45nm in UDSM range with the help of Cadence Tool and also analyzing the effect of load capacitance, transistor width and supply voltage on average power and delay of CMOS inverter on both 180nm and 45nm technology. The analysis has done with the aim to observe, the variation in delay and power with variation in transistor width, load capacitance and supply voltage in both UDSM and DSM technology CMOS inverter.