DocumentCode
1597541
Title
Acceleration of analog simulation by partial LU decomposition
Author
Davis, Albert
Author_Institution
Sch. of Comput. Sci. & Inf. Technol., Rochester Inst. of Technol., NY, USA
Volume
4
fYear
1996
Firstpage
743
Abstract
This paper presents a method for accelerating analog simulation by incrementally updating the admittance matrix, and re-solving only the part of the matrix that depends on the factors that changed. There is substantial speedup for large linear subcircuits of the type generated by RLGC extractors for interconnect analysis. It makes little if any difference for small nonlinear circuits
Keywords
analogue simulation; circuit analysis computing; electric admittance; matrix decomposition; RLGC extractor; acceleration; admittance matrix; analog simulation; interconnect; linear subcircuit; nonlinear circuit; partial LU decomposition; Acceleration; Circuit simulation; Computational modeling; Computer science; Computer simulation; Information technology; Integrated circuit interconnections; Matrices; Matrix decomposition; Roundoff errors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.542131
Filename
542131
Link To Document