Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology

In this paper, we present a comparative analysis of Double gate MOSFET (DG MOS) with the conventional bulk Si single gate MOSFET (SG MOS) by using Cadence Virtuoso simulation tool. In our observations leakage current (Ioff), delay are found to be reduced than those of the bulk Si single gate MOSFET, and the Double gate MOSFET gets same drive current based on VGS as compared to single gate MOSFET and its short channel characteristics get improved. Double gate MOSFET is mainly suggested for low power and high performance application. Total power consumption of inverter, static, dynamic circuit and latch using of double gate shows that leakage current and delay reduced by a factor of over 10x, compared with bulk Si single gate device.