DocumentCode
1597609
Title
Complete x86 instruction trace generation from hardware bus collect
Author
Bosch, P. ; Carloganu, A. ; Etiemble, D.
Author_Institution
Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
fYear
1997
Firstpage
402
Lastpage
408
Abstract
Studying architectural improvements for microprocessors and their memory hierarchies and evaluating the corresponding performance generally need trace driven simulation. Hardware is modeled, benchmark traces are generated and applied to the model and performance data is measured and analyzed. We present a hardware/software approach to collect perfect x86 execution traces using a commercial analyzer.
Keywords
computer architecture; instruction sets; performance evaluation; program diagnostics; virtual machines; architectural improvements; benchmark traces; commercial analyzer; complete x86 instruction trace generation; hardware bus collect; hardware/software approach; memory hierarchies; microprocessors; performance data; trace driven simulation; x86 execution traces; Assembly; Dynamic scheduling; Hardware; Instruments; Libraries; Logic; Performance analysis; Reduced instruction set computing; Software tools; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROMICRO 97. New Frontiers of Information Technology., Proceedings of the 23rd EUROMICRO Conference
Conference_Location
Budapest, Hungary
ISSN
1089-6503
Print_ISBN
0-8186-8129-2
Type
conf
DOI
10.1109/EURMIC.1997.617339
Filename
617339
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