Development of high performance ASICs using ACUITY image resizing engine cores

Author

Mandl, Peter ; Baker, Scott

Author_Institution

Genesis Microchip Inc., Markham, Ont., Canada

fYear

1993

Firstpage

120

Lastpage

127

Abstract

Many segments of the video/imaging industry have intensified the demand for image resizing capabilities. Systems developers generally cannot afford to invest millions of dollars in DSP research and development. If a standard image resizing IC core technology can be assessed and embedded within the system specification, highly integrated, high quality low-cost ASIC solutions can be realized. The authors present the fundamentals of digital image resizing, introduce the Genesis ACUITY technology, and describe the design and development methodology for image resizing ASICs using ACUITY cores

Keywords

FIR filters; application specific integrated circuits; circuit CAD; digital signal processing chips; image processing; integrated circuit design; two-dimensional digital filters; 2D separable FIR filters; ACUITY image resizing engine cores; design methodology; development methodology; digital image resizing; high performance ASICs; integer factor; megacells; multirate DSP; rational factor; Application specific integrated circuits; Design methodology; Digital images; Digital signal processing; Engines; Image sampling; Interpolation; Signal processing; Signal sampling; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410823

Filename

410823