Title :
Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths
Author :
Velenis, Dimitrios ; Tang, Kevin T. ; Kourtev, Ivan S. ; Adler, Victor ; Baez, Franklin ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an industrial circuit is demonstrated. The application of this technique with non-zero clock skew scheduling to the slower data paths is also described. Simulation results demonstrating the application of this technique to certain functional blocks of a high performance microprocessor are presented. A greater than 80% power savings is achieved in specific circuit blocks
Keywords :
VLSI; delays; digital integrated circuits; low-power electronics; scheduling; timing; clock skew scheduling; delay management; functional blocks; high performance integrated circuits; high performance microprocessor; industrial circuits; noncritical data paths; nonzero clock skew scheduling; onchip power dissipation; power enhancements; power reduction; Capacitance; Circuit simulation; Clocks; Delay; Energy management; Engineering management; Power dissipation; Power supplies; System-on-a-chip; Voltage;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954668
