Title :
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces
Author :
Pavlov, A. ; Béchennec, J.L. ; Etiemble, D.
Author_Institution :
Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
Abstract :
We present a methodology to evaluate performance of the memory hierarchy of PC microcomputers. This methodology is based on synthetic bus traces which allow simulation of the memory hierarchy without having to build a model of the microprocessor. As a result, the simulation is orders of magnitude faster than an instruction level one but the methodology is not valid with a dynamically scheduled superscalar microprocessor.
Keywords :
memory architecture; microcomputers; performance evaluation; storage management; virtual machines; PC microcomputers; commodity chips; desktop PC; dynamically scheduled superscalar microprocessor; memory hierarchy simulation; performance evaluation; synthetic bus traces; Costs; Discrete event simulation; Hardware; Microcomputers; Microprocessors; Operating systems; Personal communication networks; Random access memory; Scheduling; Standards organizations;
Conference_Titel :
EUROMICRO 97. New Frontiers of Information Technology., Proceedings of the 23rd EUROMICRO Conference
Conference_Location :
Budapest, Hungary
Print_ISBN :
0-8186-8129-2
DOI :
10.1109/EURMIC.1997.617340
