Title :
ASIC and DSP implementation of channel filter for 3G wireless TDD system
Author :
Vejanovski, R. ; Singh, J. ; Faulkner, M.
Author_Institution :
Telecommun. & Microelectron. Centre, Victoria Univ. of Technol., Melbourne, Vic., Australia
fDate :
6/23/1905 12:00:00 AM
Abstract :
Describes the design, simulation and implementation of a high performance low power pulse-shaping finite impulse response (FIR) filter. The filter is used for a time division duplex (TDD)-wideband code division multiple access (WCDMA) transmitter. The pulse shape filter will be implemented on a digital signal processor (DSP) and as an application specific integrated circuit (ASIC). A performance analysis and comparison using industry standard electronic design automation (EDA) tools will be carried out
Keywords :
FIR filters; application specific integrated circuits; broadband networks; cellular radio; channel bank filters; circuit CAD; code division multiple access; digital filters; digital signal processing chips; integrated circuit design; time division multiplexing; 3G wireless TDD system; ASIC; DSP; channel filter; industry standard EDA tools; performance analysis; pulse-shaping finite impulse response filter; time division duplex; wideband code division multiple access; Application specific integrated circuits; Circuit simulation; Digital signal processing; Electronic design automation and methodology; Finite impulse response filter; Multiaccess communication; Pulse circuits; Pulse shaping methods; Shape; Transmitters;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954671
