Title :
Code verification by hardware acceleration
Author :
Kohler, Helmut ; Kayser, Joerg ; Pape, Hermann ; Ruffner, Horst
Author_Institution :
IBM Lab., Boeblingen, Germany
fDate :
6/23/1905 12:00:00 AM
Abstract :
Presents the IML-code-verification methodology used for virtual poweron of IBM\´s high end servers. Virtual poweron is the process to verify, the IML (initial micro program) code weeks before the realhardware prototype is available. "Virtual-hardware" consisting of a simulation model loaded into a hardware accelerator box and a program connecting the service-element to the hardware accelerator is used instead
Keywords :
digital simulation; formal verification; logic design; IML-code-verification methodology; code verification; hardware acceleration; hardware accelerator box; high end servers; initial micro program; simulation model; virtual poweron; Acceleration; Emulation; Hardware; Life estimation; Load modeling; Portable computers; Software prototyping; Testing; Virtual prototyping; Workstations;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954674
