DocumentCode :
1598042
Title :
Real-Time Chain-Structured Synchronous Dataflow: Latency and Data Memory Requirement Formal Determination
Author :
Zhao, HuiXue ; George, Laurent ; Bourmeyster, Ivan ; Tassart, Stéphan ; Said, Laurent
Author_Institution :
CSD/MMSU/Audiolnnovation, ST Microelectron., Paris
fYear :
2009
Firstpage :
1
Lastpage :
9
Abstract :
We consider in this paper a synchronous dataflow (SDF) scheduling problem in the context of a multimedia real-time application. A SDF is in our context a chain of non-preemptive processing tasks in charge of the treatment of multimedia data blocks, denoted tokens. SDF has been wildly used in DSP (digital signal processor) design environments over the past ten years. The application relies on source, processing and sink tasks. A source task produces tokens, processing tasks process the tokens from the source down to the sink task, and a sink task consumes the tokens. Source, processing and sink tasks are executed in three different processors. As a function of the underlying hardware used to retrieve or store tokens (hard-disk or hardware machine), source and sink tasks can be periodic real-time tasks or not. Each task has an input and an output buffer filled with tokens. This model is typically used in embedded multimedia applications. We propose, in this paper, a solution to optimize both the latency of the application in charge of the treatment of the tokens and the input/output buffers used to store the tokens. We establish a necessary and sufficient condition for the feasibility of a SDF chain. We then validate our results onto a multimedia system simulator of the ST Nomadikreg platform.
Keywords :
data flow computing; multimedia computing; scheduling; data memory requirement formal determination; digital signal processor design; embedded multimedia real-time application; latency memory requirement formal determination; multimedia data blocks; processing tasks; real-time chain-structured synchronous dataflow; sink task; source task; synchronous dataflow scheduling problem; Buffer storage; Delay; Digital signal processing; Digital signal processors; Hardware; Multimedia systems; Process design; Processor scheduling; Signal design; Sufficient conditions; Data memory; Latency; Multimedia application; Real-Time Dimensioning; Synchronous Data FLow;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Autonomic and Autonomous Systems, 2009. ICAS '09. Fifth International Conference on
Conference_Location :
Valencia
Print_ISBN :
978-1-4244-3684-2
Electronic_ISBN :
978-0-7695-3584-5
Type :
conf
DOI :
10.1109/ICAS.2009.27
Filename :
4976572
Link To Document :
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