Title :
Low power nanoscale RF/analog MOSFETs
Author :
Ghosh, Dipankar ; Parihar, Mukta Singh ; Armstrong, G. Alastair ; Kranti, Abhinav
Author_Institution :
Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. Indore, Indore, India
Abstract :
The present work reports on the substantial benefits of underlap Source/Drain (S/D) design in moderately inverted nanoscale MOSFETs to significantly enhance key analog/RF performance metrics. It is demonstrated that underlap S/D design alleviates the inherent trade-offs between bandwidth, gain and linearity for low power RF CMOS nanodevices. Optimal underlap region parameters are identified and design trade-offs examined. The results are significant for RFICs with nanoscale MOSFETs in emerging technologies.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; low-power electronics; nanoelectronics; radiofrequency integrated circuits; RFIC; analog MOSFET; design trade-offs; drain design; inverted nanoscale MOSFET; low power RF CMOS nanodevice; nanoscale RF MOSFET; optimal underlap region parameter; source design; CMOS integrated circuits; CMOS technology; Logic gates; MOSFETs; Radio frequency; Semiconductor device modeling; Analog/RF; Double Gate MOSFET; Linearity; Low power;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on
Conference_Location :
Birmingham
Print_ISBN :
978-1-4673-2198-3
DOI :
10.1109/NANO.2012.6321973
