DocumentCode
1598235
Title
Integrated approach to optimized code generation for heterogeneous-register architectures with multiple data-memory banks
Author
Fröhlich, Stefan ; Wess, Bernhard
Author_Institution
Inst. of Commun. & Radio-Frequency Eng., Vienna Univ. of Technol., Austria
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
122
Lastpage
126
Abstract
This paper focuses on heterogeneous-register architectures with multiple data-memory banks. An evolutionary hybrid is introduced that combines evolutionary optimization strategies with tree techniques and list scheduling. It minimizes the execution time of the final code by jointly optimizing the schedule, selected instructions, allocated registers and data memory banks. The core of the proposed technique is a linear-time algorithm translating expression trees into optimal straight-line code segments. Topically, the proposed technique executes an order of magnitude faster than pure genetic implementations and achieves better results than with successively applied greedy techniques for the individual code generation steps. The proposed technique is well-suited to applications with stringent timing constraints
Keywords
digital signal processing chips; memory architecture; optimisation; processor scheduling; program compilers; trees (mathematics); algorithm translating expression trees; data memory banks; evolutionary optimization strategies; heterogeneous-register architectures; linear-time algorithm; list scheduling; minimisation; multiple data-memory banks; Compaction; Data engineering; Digital signal processing; Digital signal processors; Genetics; Radio frequency; Registers; Signal mapping; Signal processing algorithms; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6741-3
Type
conf
DOI
10.1109/ASIC.2001.954684
Filename
954684
Link To Document