Title :
Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control
Author :
Fasarakis, N. ; Karatsori, Theano ; Tassis, Dimitrios H. ; Theodorou, C.G. ; Andrieu, F. ; Faynot, O. ; Ghibaudo, Gerard ; Dimitriadis, C.A.
Author_Institution :
Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
Abstract :
Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.
Keywords :
MOSFET; carrier density; semiconductor device models; silicon-on-insulator; applied bias voltage; back gate control; back gate threshold voltage; buried oxide SOI MOSFET; device geometry parameter; front gate threshold voltage; fully depleted silicon-on-insulator MOSFET; ideality factors; interface ideality factor; lightly doped short channel; minimum carrier charge density; turn-on condition; ultrathin body MOSFET; Electric potential; Logic gates; MOSFET; Mathematical model; Semiconductor device modeling; Silicon; Threshold voltage; Compact model; front and back interfaces; fully depleted silicon-on-insulator (FD-SOI) ultrathin body and buried oxide thickness (UTBB) MOSFETs; ideality factor; threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2306015
