A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

Author

Cheng, Kuo-Hsing ; Chen, Yu-Jung

Author_Institution

Dept. of Electr. Eng., Tarnkam Univ., Taipei, Taiwan

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

139

Lastpage

143

Abstract

In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL has been designed and implemented by TSMC´s 0-35 μ IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cycle, and the maximum frequency of the proposed ADPLL is about 820MHz

Keywords

CMOS digital integrated circuits; binary decision diagrams; digital phase locked loops; integrated circuit design; logic design; 0-35 μ IP4M CMOS process; 0.35 micron; 14-bit control word; 3.3 V; 820 MHz; ADPLL architecture; IP4M CMOS process; Motorola; architecture; binary search decision; chip area; digital control oscillator; digital phase locked loop; frequency acquisition; operating frequency; Acceleration; Clocks; Delay; Digital control; Digital-controlled oscillators; Electronic mail; Frequency synthesizers; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6741-3

Type

conf

DOI

10.1109/ASIC.2001.954687

Filename

954687