DocumentCode
1598583
Title
Exploiting skewed state probabilities for low power state assignment
Author
Bhupathi, Lakshmikant ; Chao, Liang-Fang
Author_Institution
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume
4
fYear
1996
Firstpage
759
Abstract
We propose a new approach to solve the problem of state encoding for minimizing power consumption of multi-level implementations of FSMs. The algorithm consists of a partitioning step designed to reduce the switching activity, followed by a state encoding phase which minimizes the area. The cost functions used try to take all the causes of power dissipation into account. Skew in state probabilities is exploited to reduce the switching activity. The switching activity of all the nodes in the implementation is modeled using the concept of entropy. A literal-saving based measure is used for the area minimization step. Non-minimal length codes are used to achieve a further reduction in power. Experimental results show that, on an average, there is a 22% reduction in power compared to JEDI
Keywords
CMOS logic circuits; directed graphs; entropy codes; finite state machines; logic partitioning; minimisation of switching nets; multivalued logic; probabilistic automata; runlength codes; state assignment; CMOS circuits; FSM; area minimization; bipartite graphs; cost functions; entropy; literal-saving based measure; low power state assignment; multi-level implementations; nonminimal length codes; partitioning step; power consumption minimization; power dissipation; skewed state probabilities; state encoding; switching activity; Algorithm design and analysis; Capacitance; Chaos; Cost function; Encoding; Energy consumption; Hamming distance; Switches; Switching circuits; Terminology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.542135
Filename
542135
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