DocumentCode
1598605
Title
Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
Author
Shi Jiangyi ; Wang Mingxing ; Tian Yinghui ; Yang Zhe
Author_Institution
Dept. Microelectron., Xidian Univ., Xian, China
fYear
2012
Firstpage
1220
Lastpage
1223
Abstract
CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods are given in this paper. Then, the hardware pipelining structure of the CORDIC multiplier is put forward. Comparison results about RTL simulation results with MATLAB calculation indicate that the design is feasible and practical.
Keywords
circuit optimisation; digital arithmetic; fast Fourier transforms; multiplying circuits; CORDIC algorithm; CORDIC plural-multiplier; FFT processor; MATLAB calculation; RTL simulation; fast Fourier transform; hardware pipelining structure; optimization method; Adders; Agricultural machinery; Algorithm design and analysis; Hardware; Pipeline processing; Signal processing algorithms; Simulation; CORDIC algorithm; FFT; Pipeline structure; Plural-Multiplier;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent System Design and Engineering Application (ISDEA), 2012 Second International Conference on
Conference_Location
Sanya, Hainan
Print_ISBN
978-1-4577-2120-5
Type
conf
DOI
10.1109/ISdea.2012.500
Filename
6173427
Link To Document