Title :
FSimGEO: a test generation method for path delay fault test using fault simulation and genetic optimization
Author :
Yihe, Sun ; Qifa, Wu
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fDate :
6/23/1905 12:00:00 AM
Abstract :
Presents FSimGEO, an efficient test generation method for path delay fault test using fault simulation and genetic optimization. A parallel-vector fault simulator is introduced first, which can simulate several test vector pairs at the same time through introducing a four-valued logic and the path status graph (PSG) of the circuit structure. After this, a special genetic optimization algorithm is used to direct the process of searching and to optimize test sets generated. We have given the fitness function and genetic operators that affect the optimizing efficiency of genetic algorithm (GA) in detail. Experimental results have shown that the number of paths tested by FSimGEO is about 3.5 times that by other methods
Keywords :
circuit optimisation; delays; fault simulation; genetic algorithms; graph theory; logic testing; multivalued logic circuits; FSIMGEO; fault simulation; fitness function; four-valued logic; genetic operators; genetic optimization; optimizing efficiency; parallel-vector fault simulator; path delay fault test; path status graph; test generation method; test vector pairs; Circuit faults; Circuit simulation; Circuit testing; Clocks; Delay; Genetics; Latches; Logic circuits; Logic testing; Timing;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954702
