Title :
Design verification and DFT for an embedded reconfigurable low-power multiplier in system-on-chip applications
Author :
Margala, Martin ; Chen, Xianling ; Xu, Jian ; Wang, Hongfan
Author_Institution :
ECE Department, Rochester Univ., NY, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
A pseudo-exhaustive design verification approach is presented in this paper for an embedded low-power reconfigurable parallel multiplier in system-on-chip (SoC) applications. The proposed approach greatly reduces the size of the required test bench. Also presented are design for testability (DFT) techniques that are utilized for this multiplier to achieve high fault coverage
Keywords :
application specific integrated circuits; design for testability; fault diagnosis; formal verification; integrated circuit testing; logic testing; low-power electronics; multiplying circuits; parallel architectures; reconfigurable architectures; SoC applications; design for testability; embedded low-power reconfigurable parallel multiplier; fault coverage; pseudo-exhaustive design verification approach; test bench size; Design for testability; Digital arithmetic; Digital images; Digital signal processing; Digital signal processors; Image coding; Microprocessors; System-on-a-chip; Testing; Throughput;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954703
