Silicon nanowire devices with widths below 5 nm

This paper describes a robust process for the fabrication of highly doped Silicon-On-Insulator nanowires and devices. The process uses electron-beam lithography, low-damage dry etch and controlled thermal oxidation to deliver consistent, reproducible and reliably nanowires of nominal widths from 100 nm down to sub-5 nm etched to a depth of 55 nm in silicon. Initial electrical measurements indicate metallic behavior for the widest wires and below a particular width, the wires become depleted showing electrical behaviour consistent with Coulomb blockade at room temperature.