DocumentCode
1599267
Title
Static scheduling of hard real-time code with instruction-level timing accuracy
Author
Chung, Tai M. ; Dietz, Hank G.
Author_Institution
Sung Kyun Kwan Univ., Suwon, South Korea
fYear
1996
Firstpage
203
Lastpage
211
Abstract
In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on instruction-level compiler code scheduling and timing analysis, and can ensure the timing of control operations to within a single instruction clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed
Keywords
genetic algorithms; processor scheduling; real-time systems; timing; compiler code scheduling; genetic search algorithm; high-level language code; instruction-level; instruction-level timing accuracy; real-time systems; search space; timing analysis; timing fault; Accuracy; Clocks; Dynamic scheduling; Genetics; High level languages; Processor scheduling; Real time systems; Runtime; Safety; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time Computing Systems and Applications, 1996. Proceedings., Third International Workshop on
Conference_Location
Seoul
Print_ISBN
0-8186-7626-4
Type
conf
DOI
10.1109/RTCSA.1996.554978
Filename
554978
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