DocumentCode
1599376
Title
The Study of SoC Architecture Design Based on 32-bit Embedded RISC Processor
Author
Yuan Ying ; Wu Wuchen ; Hou Ligang ; Geng Shuqin ; Zhou Zhonghua ; Liu Qi
Author_Institution
Beijing Univ. of Technol., Beijing, China
fYear
2012
Firstpage
1339
Lastpage
1342
Abstract
As a important step in SoC design, good architecture design is the foundation to ensure the final structure to meet the design specifications. In paper, the minimal SoC system used for performance compare between basic architectures is defined, which is consisted of embedded processor, on chip bus, on chip memory and IP (GPIO). Then six SoC architecture based on 32 bit embedded RISC processor is studied, and comparison and analysis are discussed.
Keywords
embedded systems; reduced instruction set computing; system buses; system-on-chip; 32-bit embedded RISC processor; GPIO; IP; SOC architecture design; design specification; minimal SOC system; on chip bus; on chip memory; system-on-chip; word length 32 bit; Field programmable gate arrays; IP networks; Power demand; Reduced instruction set computing; System-on-a-chip; Table lookup; Architecture design; Embedded RISC processor; minimal SoC system;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent System Design and Engineering Application (ISDEA), 2012 Second International Conference on
Conference_Location
Sanya, Hainan
Print_ISBN
978-1-4577-2120-5
Type
conf
DOI
10.1109/ISdea.2012.431
Filename
6173456
Link To Document