Title :
Reducing the cost of scan in deep sub-micron designs
Author :
Rahimi, Kambiz ; Soma, Mani
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
Proposes a method for reducing the cost of scan by assigning scan elements to multiple scan chains after placements are determined. An algorithm based on Gale-Shapley stable marriage is proposed. Experiments with ISCAS89 benchmarks show that the algorithm reduces scan chain lengths by 55 to 92 percent
Keywords :
VLSI; boundary scan testing; circuit optimisation; design for testability; flip-flops; logic testing; simulated annealing; Gale-Shapley stable marriage; ISCAS89 benchmarks; cost of scan; deep sub-micron designs; design for testability; multiple scan chains; placements; scan chain lengths; scan elements; Automatic test pattern generation; Capacitance; Circuit testing; Costs; Design for testability; Design optimization; Kernel; Logic programming; Registers; Routing;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954735
