Testability of ECL circuits in a BiCMOS process

Testability analysis and reliability considerations of emitter coupled logic (ECL) circuits in a BiCMOS environment are discussed. The effects of physical defects on basic ECL logic gates, reference voltage circuits, CMOS-ECL and ECL-CMOS translator circuits are investigated. The faults induced by the defects have been analyzed and classified into two groups: logical faults and performance degradation faults such as delay, current, and noise margin faults. It is shown that a specific combination of testing methods is required to achieve the highest fault coverage in both the ECL gates and the level translator circuits. Also, defects that lead to a severe performance degradation are identified for each of the test circuits