Title :
Testability of ECL circuits in a BiCMOS process
Author :
Esonu, M.O. ; Al-Khalili, D. ; Rozon, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada
Abstract :
Testability analysis and reliability considerations of emitter coupled logic (ECL) circuits in a BiCMOS environment are discussed. The effects of physical defects on basic ECL logic gates, reference voltage circuits, CMOS-ECL and ECL-CMOS translator circuits are investigated. The faults induced by the defects have been analyzed and classified into two groups: logical faults and performance degradation faults such as delay, current, and noise margin faults. It is shown that a specific combination of testing methods is required to achieve the highest fault coverage in both the ECL gates and the level translator circuits. Also, defects that lead to a severe performance degradation are identified for each of the test circuits
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; circuit analysis computing; design for testability; emitter-coupled logic; fault diagnosis; integrated circuit reliability; integrated circuit testing; logic testing; reference circuits; BiCMOS; CMOS-ECL; ECL circuits; ECL-CMOS; current; delay; logical faults; noise margin faults; performance degradation faults; reference voltage circuits; reliability; testability analysis; translator circuits; BiCMOS integrated circuits; Circuit faults; Circuit testing; Coupling circuits; Degradation; Logic circuits; Logic gates; Logic testing; Performance analysis; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410831
