Constructive and local search heuristic techniques for FPGA placement

The logic capacity of FPGAs has increased so rapidly in the last decade (up to 40-million gates) that it takes a considerable amount of time to synthesize and compile these circuits. These prohibitively long compile times may adversely affect the instant manufacturability of FPGAs and become intolerable to users seeking very high compile speed. The paper presents two novel placement heuristic algorithms that significantly reduce the amount of computation time required to achieve acceptable-quality placements. The first algorithm is a cluster seed search technique (CSS) that is considered to be a constructive based method and can be implemented in trivial time compared with other placement algorithms. The second algorithm is an enhancement of local search, and is implemented as a simple local search (SLS) and immediate neighborhood local search (INLS). Both techniques achieve reasonably good solutions quickly.