Title :
Towards high-k integration with III-V channels: Interface optimization of high pressure sputtered gadolinium oxide on indium phospide
Author :
San Andres, E. ; Pampillon, M.A. ; Canadilla, C. ; Feijoo, P.C. ; del Prado, A.
Author_Institution :
Dept. de Fis. Aplic. III (Electr. y Electron.), Univ. Complutense de Madrid, Madrid, Spain
Abstract :
We studied the electrical properties of metal-oxide-semiconductor devices based on Gd2O3 deposited on InP by high pressure sputtering and a novel plasma oxidation process. The resulting devices show fully functional capacitance curves., indicating an unpinned Fermi level. The samples were annealed in forming gas at temperatures up to 550°C. We studied the interface trap density of the devices. We found out that with increasing annealing temperature the defect content decreases but at 550°C the capacitance drops and the leakage current increases., indicating a dielectric degradation.
Keywords :
Fermi level; III-V semiconductors; MIS devices; annealing; defect states; gadolinium compounds; high-k dielectric thin films; high-pressure effects; indium compounds; leakage currents; optimisation; plasma materials processing; sputter deposition; Gd2O3-InP; III-V channels; InP; annealing; defect content; dielectric degradation; electrical properties; forming gas; functional capacitance curves; high pressure sputtering; high-k integration; interface optimization; interface trap density; leakage current; metal-oxide-semiconductor devices; plasma oxidation; temperature 550 degC; unpinned Fermi level; Annealing; Capacitance; Frequency measurement; Indium phosphide; Logic gates; Plasma temperature; III-V; gadolinium oxide; high-k; indium phosphide; plasma oxidation; sputtering;
Conference_Titel :
Electron Devices (CDE), 2013 Spanish Conference on
Conference_Location :
Valladolid
Print_ISBN :
978-1-4673-4666-5
Electronic_ISBN :
978-1-4673-4667-2
DOI :
10.1109/CDE.2013.6481333
