Title :
A seamless parallel algorithm for full chip compaction
Author :
Shao, Jianhua ; Chen, Richard M M
Author_Institution :
Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon, Hong Kong
Abstract :
A parallel compaction algorithm which is capable of full chip compaction is presented. Each partitioned part is compacted by individual computer concurrently, and an interface graph scheme is used to ensure that the final result is exactly the same as that of the full chip layout compacted as a whole. Experimental results show that significant speedup is achieved
Keywords :
circuit layout CAD; integrated circuit layout; parallel algorithms; chip layout; full chip compaction; interface graph scheme; parallel compaction algorithm; seamless parallel algorithm; Compaction; Computer interfaces; Computer networks; Concurrent computing; Heuristic algorithms; Magnetic heads; Master-slave; Parallel algorithms; Partitioning algorithms; Tail;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.542142
