• DocumentCode
    1600804
  • Title

    Static timing analyzer with source/drain identification by non-Z procedure

  • Author

    Kuribayashi, Mototaka ; Takeuchi, Hideki ; Tsujimoto, Junichi ; Kuroiwa, Kentaro ; Tonooka, Yasuhiro

  • Author_Institution
    Semicond. DA, Toshiba Corp., Kawasaki, Japan
  • Volume
    4
  • fYear
    1996
  • Firstpage
    791
  • Abstract
    This paper describes an efficient signal flow determination algorithm for static timing analysis at the transistor-level. The false path problem on the transistor-level is closely related to determining transistors´ signal flow. The proposed non-Z procedure greatly contributes to solve such problems. According to the experimental results, the algorithm has determined signal flow direction for nearly 100% of transistors. High percentage of signal flow determination not only contribute to eliminating false paths, but also cuts down on timing analysis running time
  • Keywords
    VLSI; circuit analysis computing; digital integrated circuits; timing; digital VLSI circuits; false path problem; non-Z procedure; signal flow determination algorithm; source/drain identification; static timing analyzer; transistor-level; Algorithm design and analysis; Circuit analysis; Circuit simulation; Multiplexing; SPICE; Semiconductor device testing; Signal analysis; TV; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    0-7803-3073-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1996.542143
  • Filename
    542143